The present invention relates to a semiconductor packaging technology, and more particularly, to a stacked semiconductor package.
In the semiconductor industry, packaging technologies for semiconductor devices have continuously been developed to meet the demands toward miniaturization and high capacity. Recently, various technologies for a stacked semiconductor package capable of meeting the demands toward miniaturization, high capacity and mounting efficiency have been developed.
The term “stack” referred to in the semiconductor industry means a technology of vertically placing at least two semiconductor chips or semiconductor packages. In the case of a memory device, by using the stack technology, it is possible to realize a product having a memory capacity greater than that achievable through general semiconductor integration processes, and mounting area utilization efficiency can be improved.
However, in order to manufacture a stacked semiconductor package, semiconductor chips should be vertically placed one by one. As the number of semiconductor chips to be stacked increases, a time required to manufacture a stacked semiconductor package is lengthened and the number of necessary processes increases. Also, if a failure occurs in any one of semiconductor package manufacturing processes, a corresponding semiconductor package is sorted to be a bad product. Thus, in a stacked semiconductor package, the possibility of a fail to occur increases with the number of chips/packages. For example, if sixteen chips are to be stacked, each of a chip attaching process and a wire bonding process should be performed sixteen times. Hence, a package manufacturing time is lengthened, and if a failure occurs even in any one of a number of processes, a corresponding semiconductor package is sorted to be a bad product. Namely, in a stacked semiconductor package, the possibility of a failure becomes substantial.
Further, since all stacked semiconductor chips should be connected with one substrate, it may be difficult or substantially impossible to design a substrate due to limitations in terms of positions of bonding pads in the semiconductor chips, positions of the semiconductor chips in the substrate, presence of a controller chip, and the area of the substrate. For example, connection pads of the substrate may be formed only on both sides of the semiconductor chips, and it may be impossible to form connection pads which are connected with the controller chip.
Moreover, if the number of semiconductor chips to be stacked increases, bonding wires for connecting the semiconductor chips with the substrate needs to be long. In this regard, if the lengths of the bonding wires increase, the probability of defects such as a short between the bonding wires or wire sweeping increases. When a test is performed after the manufacture of a package is completed, if a failure occurs in one semiconductor chip, all the other semiconductor chips that may be good in the package also need to be discarded, leading to waste of good semiconductor chips as well as waste of production time.